//Title：     reg_file
//Author:     Yang Siyang
//Description:RV64 CPU的寄存器堆
//---------------------------------------------------------
`include "defines.v"
module reg_file (clk,rst,r_addr_1,r_addr_2,r_en_1,r_en_2,w_addr,w_en,w_v,r_v_1,r_v_2);
    input clk,rst; 
    input [`REG_ADDR_BUS] r_addr_1;//5位寄存器地址
    input [`REG_ADDR_BUS] r_addr_2;//5位寄存器地址
    input r_en_1,r_en_2;		   //读寄存器使能信号，现在用不到
    input [`ADDR_BUS]w_addr;	   //写地址
    input w_en;					   //写使能信号
    input [`REG_BUS] w_v;	       //要写入的值
	//输出
    output [`REG_BUS] r_v_1;	//读出值1
    output [`REG_BUS] r_v_2;	//读出值2
//32 registers---------------------------------------------------------
	reg [`REG_BUS] regs[0 : 31];
	
	always @(posedge clk) 
	begin
		if ( rst == 1'b1 )//复位
		begin
			regs[ 0] <= `ZERO_DOUBLE_W;
			regs[ 1] <= `ZERO_DOUBLE_W;
			regs[ 2] <= `ZERO_DOUBLE_W;
			regs[ 3] <= `ZERO_DOUBLE_W;
			regs[ 4] <= `ZERO_DOUBLE_W;
			regs[ 5] <= `ZERO_DOUBLE_W;
			regs[ 6] <= `ZERO_DOUBLE_W;
			regs[ 7] <= `ZERO_DOUBLE_W;
			regs[ 8] <= `ZERO_DOUBLE_W;
			regs[ 9] <= `ZERO_DOUBLE_W;
			regs[10] <= `ZERO_DOUBLE_W;
			regs[11] <= `ZERO_DOUBLE_W;
			regs[12] <= `ZERO_DOUBLE_W;
			regs[13] <= `ZERO_DOUBLE_W;
			regs[14] <= `ZERO_DOUBLE_W;
			regs[15] <= `ZERO_DOUBLE_W;
			regs[16] <= `ZERO_DOUBLE_W;
			regs[17] <= `ZERO_DOUBLE_W;
			regs[18] <= `ZERO_DOUBLE_W;
			regs[19] <= `ZERO_DOUBLE_W;
			regs[20] <= `ZERO_DOUBLE_W;
			regs[21] <= `ZERO_DOUBLE_W;
			regs[22] <= `ZERO_DOUBLE_W;
			regs[23] <= `ZERO_DOUBLE_W;
			regs[24] <= `ZERO_DOUBLE_W;
			regs[25] <= `ZERO_DOUBLE_W;
			regs[26] <= `ZERO_DOUBLE_W;
			regs[27] <= `ZERO_DOUBLE_W;
			regs[28] <= `ZERO_DOUBLE_W;
			regs[29] <= `ZERO_DOUBLE_W;
			regs[30] <= `ZERO_DOUBLE_W;
			regs[31] <= `ZERO_DOUBLE_W;
		end
		else
		begin //write
			if ((w_en == 1'b1) && (w_addr != 5'h00))//write enable   not in regs[0]?
			begin 
                regs[w_addr] <= w_v;
			end
		end
	end
//---------------------------------------------------------
    //read 1
    always @(*) begin
		if (rst == 1'b1)                //reset
			r_v_1 = `ZERO_DOUBLE_W;
		else// if (r_en_1 == 1'b1)        //read 1 enable
			r_v_1 = regs[r_addr_1];
		//else
		//	r_v_1 = `ZERO_DOUBLE_W;   //no enable
	end
	//read 2
	always @(*) begin
		if (rst == 1'b1)                //reset
			r_v_2 = `ZERO_DOUBLE_W;
		else //if (r_en_2 == 1'b1)        //read 2 enable
			r_v_2 = regs[r_addr_2];
		//else
		//	r_v_2 = `ZERO_DOUBLE_W;   //no enable
	end

endmodule